ZISC, the merger of 2 concepts

Non linear classifier…

  • 1974 – Compound classifier invented by Bruce Batchelor
  • 1982 – Restricted Coulomb Energy classifier, derived by Leon Cooper (Nobel prize for supraconductivity)

…on a parallel hardware architecture

  • 1984 – CERN’s UA1 experiment is lead by Nobel prize winner Carlo Rubbia. Guy Paillet DataSud Systems designs a parallel architecture of 60 CPU’s/Memory on same VME  bus.

A promise…

  • 1988 – DARPA Neural Network Study: “The technology is not mature for widespread practical applications, since computer simulation are the primary methods of implementation.”

…come true

  • 1993 – ZISC (Zero Instruction Set Computer with  36 neurons designed  and patented by IBM France and Guy Paillet

ZISC

ZISC stands for Zero Instruction Set Computer and is a neural network chip which was invented and patented jointly by a team of engineers at IBM France and Guy Paillet in 1993. The ZISC chip was manufactured by IBM between 1993 and 1999.

Its sucessor, the CM1K chip, was designed by the team at General Vision and released in August 2007.

The CM1K chip features significative improvements over the ZISC78 chip.

Feature
ZISC78
CM1K
Neurons per chip
78
1024
Neuron memory
64 bytes
256 bytes
Radial Basis Function
Yes
Yes
K Nearest Neighbor
Yes
Yes
Parallel bus width
74 lines
28 lines
Packaging
LQFP 100
TQFP 100
Dye size
4.66  x 4.66 mm
8 x 8 mm
Operating clock frequency (max)
33 Mhz
27 Mhz
Power supply
3.3V for IO;
2.5 V for core
3.3V for IO;
1.2 V for core
Power saving mode
Yes
Yes
Neuron Identifier register
24-bit
Index Component register
8-bit
I2C serial access (100, 400 Kbit per second)
2 lines
Recognition stage with direct digital bus input
Yes (11 lines)
Digital input bus clock frequency (max)
40 Mhz
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