Zero Instruction Set Computer

The Zero Instruction Set Computer (ZISC) is a neural network chip which was invented and patented jointly by a team of engineers at IBM France and Guy Paillet in 1993. The ZISC chip was manufactured by IBM between 1993 and 1999. Its successor, the CM1K chip, was designed by the team at General Vision and released in August 2007.

Non linear classifier…

  • 1974 – Compound classifier invented by Bruce Batchelor
  • 1982 – Restricted Coulomb Energy classifier, derived by Leon Cooper (Nobel prize for supraconductivity)

…on a parallel hardware architecture

  • 1984 – CERN’s UA1 experiment is lead by Nobel prize winner Carlo Rubbia. Guy Paillet DataSud Systems designs a parallel architecture of 60 CPU’s/Memory on same VME  bus.


A wish…

  • 1988: DARPA Neural Network Study: “The technology is not mature for widespread practical applications, since computer simulation are the primary methods of implementation.”

…come true

  • 1993: ZISC (Zero Instruction Set Computer with  36 neurons designed  and patented by IBM France and Guy Paillet.
  • 2007-2009: Its successor, the CM1K chip, is designed by the team at General Visionand release in production two years later.

ZISC78 and CM1K comparative chart

Feature ZISC78 CM1K
Neurons per chip 78 1024
Neuron memory 64 bytes 256 bytes
Distance register 16 bit 16 bit
Category value 15 bit 15 bit
Degenerated neuron flag Yes Yes
Context values 7 bit 7 bit
Norms to calculate distance L1 and Lsup L1 and Lsup
Radial Basis Function Yes Yes
K Nearest Neighbor Yes Yes
Parallel bus width 74 lines 28 lines
Packaging LQFP 100 TQFP 100
Dye size 4.66  x 4.66 mm 8 x 8 mm
Operating clock frequency (max) 33 Mhz 27 Mhz
Power supply 3.3V for IO;2.5 V for core 3.3V for IO;1.2 V for core
Power saving mode Yes Yes
Neuron Identifier register 24-bit
Index Component register 8-bit
I2C serial access (100, 400 Kbit per second) 2 lines
Recognition stage with direct digital bus input 10 lines for signal11 lines for video
Digital input bus clock frequency (max) 40 Mhz